1. Field
The present disclosure relates generally to a memory interface circuit, and more particularly, to a reconfigurable memory interface circuit to support a built-in memory scan chain.
2. Background
To enable an automatic test pattern generation (ATPG) scan, a memory interface circuit within a memory may include scan latches that are used only for the ATPG scan. Including the scan latches increases an area overhead of the memory, as the scan latches are utilized only for the ATPG scan. Accordingly, methods and apparatuses are needed for enabling the ATPG scan without including the scan latches in the memory. Including the scan latches in the memory increases an area overhead of the memory.